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GE28F640W18BD60 - Intel GE28F640W18BD60 Wireless Flash Memory Simple Type: Memory Module

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Intel GE28F640W18BD60 Wireless Flash Memory Simple Type: Memory Module

The Intel Wireless Flash Memory (W18) device with flexible multi-partition dual operation, provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs. Combining high read performance with flash memory’s intrinsic nonvolatility, theW18 device eliminates the traditional system-performance paradigm of shadowing redundant code memory from slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases reliability and reduces overall system power consumption and cost. The W18 device’s flexible multi-partition architecture allows programming or erasing to occur in one partition while reading from another partition. This allows for higher data write throughput compared to single partition architectures. The dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. The designer can also choose the size of the code and data partitions via the flexible multi-partition architecture.

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  • 11 ns Burst-Mode Read Speed
  • 20 ns Page-Mode Read Speed
  • 4-, 8-, 16-, and Continuous-Word Burst Mode Reads
  • 60 ns Initial Access Read Speed
  • Blocks, across all partition boundaries
  • Burst and Page Mode Reads in all
  • Burst frequency at 66 MHz
  • Burst Suspend Feature
  • Enhanced Factory Programming at 3.1 µs/word (typ.for 0.13 µm)
  • High Performance Read-While-Write/Erase


  • ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit:A[22:0]
  • ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
  • CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps. De-asserting CE# deselects the device, places it in standby mode, and tri-states all outputs.
  • CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and increments an internal address generator. During synchronous read operations, addresses are latched on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.
  • DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, status register, protection register, and configuration code reads. Data pins float when the chip or outputs are deselected. Data is internally latched during writes.
  • DEVICE POWER SUPPLY: Writes are inhibited at VCC = VLKO. Device operations at invalid VCC
  • ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
  • GROUND: Pins for all internal device circuitry must be connected to system ground.
  • OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle. When OE# is deasserted, data outputs are placed in a high-impedance state.
  • OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to VCC.
  • RESET: When low, RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. de-asserting RST# enables normal operation and places the device in asynchronous read-array mode.
  • WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be asserted-high or asserted-low based on bit 10 of the Configuration Register. WAIT is tri-stated if CE# is deasserted. WAIT is not gated by OE#.
  • WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the rising edge of WE#.
  • WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software.



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